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Return add_vec(current_integration, mul(error,dt),x"0000") current_integration := add_vec(current_integration, mul(error,dt),x"0000") Variable derivative_val: std_logic_vector(15 downto 0) ĭerivative_val := div(sub(error,previous_error),dt) įunction integration(error,dt:in std_logic_vector(7 downto 0) current_integration :in std_logic_vector(15 downto 0) reset : in std_logic) return std_logic_vector is Return std_logic_vector(to_unsigned(quotient,16)) įunction derivative(error, previous_error, dt :in std_logic_vector(7 downto 0)) return std_logic_vector is V_TEST_VARIABLE2 := v_TEST_VARIABLE2 - v_TEST_VARIABLE1 V_TEST_VARIABLE1 := v_TEST_VARIABLE1 - v_TEST_VARIABLE2 Įxit when ((v_TEST_VARIABLE1 - v_TEST_VARIABLE2)>0) Return std_logic_vector(to_unsigned(product,16)) įunction div(num1, num2 : in std_logic_vector(7 DOWNTO 0)) return std_logic_vector isĮxit when ((v_TEST_VARIABLE2 - v_TEST_VARIABLE1)>0) Return std_logic_vector(to_unsigned(difference,8)) įunction mul(num1,num2 : in std_logic_vector(7 DOWNTO 0)) return std_logic_vector isįor n_times in 1 to v_TEST_VARIABLE2 loop Return std_logic_vector(to_unsigned(sum,32)) įunction sub(num1, num2: in std_logic_vector(7 downto 0)) return std_logic_vector isĭifference := v_TEST_VARIABLE1 - v_TEST_VARIABLE2 Sum:= v_TEST_VARIABLE1+ v_TEST_VARIABLE2 + v_TEST_VARIABLE3 v_TEST_VARIABLE1:= v_TEST_VARIABLE1 + '1' for n_times2 in 1 to v_TEST_VARIABLE3 loop v_TEST_VARIABLE1: = v_TEST_VARIABLE1 + '1' for n_times1 in 1 to v_TEST_VARIABLE2 loop V_TEST_VARIABLE3 := to_integer(unsigned(num3 )) V_TEST_VARIABLE2 := to_integer(unsigned(num2)) V_TEST_VARIABLE1 := to_integer(unsigned(num1)) functionsįunction add_vec(num1,num2,num3: in std_logic_vector(15 downto 0)) return std_logic_vector is
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Output :out std_logic_vector(31 downto 0) ) Port( error ,Kp, Ti, Td ,dt: in std_logic_vector(7 downto 0)
MODELSIM PE 10.4A INSTALL CODE
Fatal error in modelsim during simulation - vhdl This is my main code in VHDL: